Sr. Principal Design Engineer
Core
Designing low power, low voltage, and high performance SRAM/Register File circuits and macros for semiconductor applications.
Role type
Senior IC circuit design engineer (memory)
Builds
Full-custom SRAM macros, sense amplifiers, and self-timed circuits
Domain
Semiconductor / VLSI / Memory
Deliverable
production ML models | product features
Required skills
CMOS device physics, transistor sizing, memory cell stability, SPICE simulation, process corner analysis, physical design verification, Python scripting, Perl scripting
Preferred skills
FinFET manufacturing rules, layout supervision, post-silicon debugging
Technologies
Cadence Virtuoso, SPICE
Responsibilities
Build full-custom or compiler-based SRAM macros and self-timed circuits; Run SPICE simulations to analyze timing, power, and Static Noise Margin across process corners; Direct physical design and layout teams to handle process variability; Support post-silicon testing and troubleshooting hardware failures
Seniority
Senior, hands-on IC
