Intern: Application Engineering - Formal Verification
Core
Intern providing technical support and root cause analysis for RTL-level formal verification tools, specifically the Jasper platform, to enable customer deployment of industry-leading technology.
Role type
Intern, Application Engineering (Formal Verification)
Builds
Customer support workflows and R&D fix validation for digital functional verification tools
Domain
Semiconductor design automation / Electronic design automation (EDA)
Deliverable
client delivery
Required skills
Formal Verification methodologies, RTL verification (Verilog/VHDL), TCL scripting, Root cause analysis, Test case execution, Documentation authoring
Preferred skills
Python scripting, University knowledge of formal verification tools
Technologies
Jasper, Xcelium, Palladium, Protium, VIPs, TCL, Python, Verilog, VHDL
Responsibilities
Provide technical support to customers and field personnel in RTL verification solutions focused on the Jasper tool; Conduct root cause analysis and provide resolution to customer technical issues; Run customer test cases to verify problems, create workarounds when possible, test and deliver R&D fixes; Close collaboration with R&D on issues using established protocols; Author application notes and help provide feedback on documentation
Seniority
Intern, mentored IC