Intern
Core
Implementing microprocessor cores and multiprocessor sub-systems in RTL for Xtensa processors, focusing on timing, area, and power goals for intelligent IoT devices.
Role type
Design Engineering Intern (Logic Design)
Builds
Configurable and extensible processor cores and DSPs for ML/AI applications at the edge.
Domain
Semiconductor design IP, electronic design automation, hardware verification.
Deliverable
production ML models | product features | infrastructure
Required skills
Digital Design Fundamentals, Verilog RTL implementation, Tcl scripting, Perl scripting, shell scripting, synthesis, place & route, timing analysis, area optimization, power optimization, functional diagnostics, coverage analysis.
Preferred skills
Exposure to design automation tools.
Responsibilities
Implement micro-architecture in Verilog RTL, simulate and debug functions, run EDA scripts to meet timing/area/power goals, assist with test plans and functional diagnostics, debug failures, analyze coverage information.
Seniority
Intern
