Senior Digital Design Engineer
Core
Develop and verify RTL for digital blocks and subsystems within mixed-signal SoCs for high-performance power systems in data centers and energy infrastructure.
Role type
Senior IC digital design engineer (ASIC/SoC)
Builds
Mixed-signal SoCs for power, connectivity, and analytics solutions
Domain
Semiconductor / Data Center & Energy
Deliverable
production ML models | product features
Required skills
RTL development, verification, synthesis, static timing analysis, DFT insertion, Python scripting, Verilog/SystemVerilog
Preferred skills
FPGA prototyping, system-level modeling, power system components knowledge, AMBA/I²C/SPI protocols
Technologies
Genus, Innovus, Tempus, Conformal, Verilog, SystemVerilog, Python, C
Responsibilities
Develop and verify RTL for digital blocks and subsystems; Perform synthesis, static timing analysis, and support DFT; Collaborate with analog, firmware, and validation teams; Assist with silicon bring-up and debug; Contribute to methodology improvements and automation initiatives
Seniority
Senior, hands-on IC
