Staff Engineer, Digital design engineering
Core
Building and maintaining FPGA-based prototyping platforms for complex SoC ASIC designs, enabling early software development and RTL validation.
Role type
Senior IC FPGA Design and Implementation Engineer
Builds
FPGA prototyping platforms and automated build infrastructure for ASIC validation
Domain
Semiconductor / FPGA / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
FPGA design, Vivado tooling, ASIC-to-FPGA porting, timing closure, clock architecture design, automated build scripting, embedded C programming
Preferred skills
Hardware lab experience, Intel/Quartus flows, AXI/AHB/APB bus protocols, ARM Cortex-M subsystems, debug infrastructure
Technologies
Vivado, Xilinx UltraScale+, proFPGA, TCL, Python, SystemVerilog, Embedded C, GCC ARM toolchain, Oscilloscope, logic analyzer, JTAG debugger
Responsibilities
Develop and maintain FPGA prototyping platforms for ASIC designs; Own the FPGA synthesis, implementation, and timing closure flow; Port ASIC RTL to FPGA including clock tree adaptation and memory model replacement; Develop and maintain automated build scripts for Vivado; Debug synthesis/implementation failures and optimize QoR; Collaborate with ASIC design teams to integrate new RTL drops; Interface with FPGA vendor on tool issues; Develop clock management architectures; Support silicon validation and firmware teams with FPGA images; Develop and execute bare-metal test programs
Seniority
Senior, hands-on IC
