High Level Synthesis (HLS) Compiler Engineer (Intern))
Core
Develop and maintain HLS compiler infrastructure to translate high-level C/C++ code into efficient hardware implementations for FPGA/ASIC.
Role type
Intern High Level Synthesis (HLS) Compiler Engineer
Builds
HLS compiler tools and optimization passes for hardware synthesis
Domain
Semiconductor / FPGA / Compiler Technology
Deliverable
production ML models
Required skills
C/C++ programming, compiler concepts (parsing, code generation, optimization), digital logic design fundamentals
Preferred skills
HLS compilers and hardware synthesis knowledge, MLIR/LLVM/Clang familiarity, HLS tools (Xilinx Vivado HLS, Intel HLS), Verilog/VHDL, Git
Responsibilities
Assist in developing HLS compiler infrastructure, implement compiler passes and code transformations, analyze and improve C/C++ to hardware description language compilation flow, research compiler technology for AI workloads, integrate and test new features, debug and validate compiler outputs, document work
Seniority
Intern
