HLD Validation Technical Lead
Core
Researches, designs, develops, and optimizes software tools and frameworks for Field Programmable Gate Arrays (FPGA), including compilers, flows, and abstractions for domains like deep learning and DSP.
Role type
Senior IC FPGA software tool validation lead
Builds
FPGA software tools, compilers, flows, assemblers, models, runtimes, and firmwares
Domain
Semiconductor hardware design and FPGA software tooling
Deliverable
production ML models
Required skills
FPGA architecture knowledge, tool flow expertise (design entry to hardware execution), validation strategy design, scripting/automation (Python, Perl, Tcl, shell), cross-layer debugging, risk-based analysis
Preferred skills
HLD tool experience (high-level synthesis, DSP-oriented design, AI-oriented FPGA tools), Altera/Intel Quartus Prime, Verilog/VHDL, board-level testing/SoC integration, Linux/Windows test environments, performance characterization, UI automation (Playwright, Selenium)
Responsibilities
Develop and optimize compilers and flows coupled to FPGA silicon; design software abstractions for acceleration; create validation strategies, test plans, and regression suites; debug cross-layer software and FPGA issues; communicate findings to stakeholders
Seniority
Senior, hands-on IC with leadership
