FPGA Development Tools Engineer - Placer
Core
Developing and optimizing FPGA placement algorithms within the compiler toolchain to improve timing, congestion, resource utilization, and design quality.
Role type
Senior IC FPGA development tools engineer (placement algorithms)
Builds
FPGA compiler toolchain (Quartus) and placement capabilities
Domain
Semiconductor / EDA / FPGA
Deliverable
production ML models | product features
Required skills
C++, algorithm design, timing analysis, compiler flow integration, performance optimization, debugging
Preferred skills
Verilog, Python, TCL
Technologies
Quartus, C++, Verilog, Python, TCL
Responsibilities
Design and implement FPGA placement algorithms; Contribute to end-to-end FPGA compilation flow; Optimize runtime performance and scalability; Develop timing-aware placement strategies; Analyze placement quality and timing bottlenecks; Integrate placement capabilities into compiler infrastructure
Seniority
Mid-to-Senior, hands-on IC
