IC Design AI/ML Silicon Debug & Yield Engineer
Core
Building AI/ML engines to ingest massive scan failure data and process parameters to automate yield diagnostics and drive aggressive yield ramps.
Role type
Senior IC Design AI/ML Silicon Debug & Yield Engineer
Builds
AI-driven diagnostic pipelines and predictive yield models for semiconductor manufacturing
Domain
Semiconductor manufacturing (FinFET nodes) + Machine Learning
Deliverable
production ML models
Required skills
ASIC design (logic, memory, PLL/Analog, DFT, DFM), Python (Pandas, Scikit-Learn, PyTorch/TensorFlow), SQL, big data environments (Spark, Snowflake), pattern recognition, clustering, regression modeling, semiconductor manufacturing processes
Preferred skills
Deep understanding of scan compression, BIST, ATPG patterns, shmoo plots, IR drop, crosstalk, industry-standard yield management systems (PDF Solutions, Synopsys YieldExplorer, Cadence Clarity)
Technologies
Python, SQL, Spark, Snowflake, PyTorch, TensorFlow, Scikit-Learn
Responsibilities
Develop ML models to automate classification of scan failures; Integrate high-dimensional data to predict yield excursions; Analyze interplay between design marginalities and manufacturing variations; Evaluate and implement AI-based EDA tools for root-cause analysis; Act as translator between Fab, Design, and Test teams using data to prove silicon divergence from simulation
Seniority
Senior, hands-on IC