Senior Design Automation Engineer - Front End Design Verification
Core
Building and maintaining core automation infrastructure for Altera's FPGA design flows from RTL to GDSII to scale internal design productivity.
Role type
Senior Design Automation Engineer (Front End Design Verification)
Builds
Highly automated, reliable, and efficient flow systems for next-generation FPGA products
Domain
Semiconductor / FPGA Design Automation / EDA
Deliverable
production ML models | infrastructure
Required skills
Front End RTL and Design Verification EDA tools, FPGA/ASIC design flows, AI/ML-driven features within EDA tools, Unix/Linux environments, Python, Tcl, Shell, flow automation tools
Preferred skills
Front End Pre-Silicon design verification flows, advanced EDA tool features (Lint/CDC/RDC), large-scale SoC or IP development environments
Technologies
VCS, Xcelium, SpyGlass
Responsibilities
Develop and support advanced design automation flows and methodologies for digital semiconductor design; Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools; Evaluate, integrate, and enhance EDA tools to improve design productivity; Automate repetitive design tasks to deliver robust and scalable solutions; Collaborate with design and verification teams to identify workflow bottlenecks and implement process improvements; Work with internal teams and external EDA vendors to resolve tool issues and influence roadmaps
Seniority
Senior, hands-on IC
