Staff Design Verification Infrastructure Engineer - VIPs and Testbench
Core
Architecting and developing reusable verification infrastructure (VIPs, AIPs, testbenches) using System Verilog, UVM, Chisel, and Scala to support SiFive's chip design verification efforts.
Role type
Staff Design Verification Infrastructure Engineer
Builds
Reusable verification platform components, test harnesses, stimulus generators, and scoreboards for RISC-V processors
Domain
Semiconductor chip design / RISC-V architecture / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Chisel, Scala, Software Engineering, Testbench Architecture, Verification Methodology
Preferred skills
Python, EDA tools, DevOps, CI/CD pipelines
Technologies
System Verilog, UVM, Chisel, Scala, Python, EDA tools
Responsibilities
Architect and maintain the Verification Platform infrastructure; Develop Verification Platform libraries for expressing verification intent; Develop VIPs, AIPs, and testbench components; Create test plans and verify release of components; Educate verification teams on best practices
Seniority
Staff, hands-on IC with architectural leadership
