Senior Design Verification Engineer
Core
Own block- and subsystem-level design verification for advanced out-of-order (OoO) CPU cores, focusing on execution pipelines, memory systems, and coherence protocols.
Role type
Senior IC design verification engineer (CPU micro-architecture)
Builds
Verified OoO CPU cores for high-performance compute platforms
Domain
Semiconductor / CPU Design / Computer Architecture
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, CPU micro-architecture knowledge, constrained-random verification, coverage-driven verification, SVA assertions, simulator debugging
Preferred skills
Experience with speculative execution flows, memory consistency models, cache hierarchy verification
Technologies
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, DVE
Responsibilities
Develop and maintain SystemVerilog/UVM testbenches with agents, monitors, and scoreboards; Define and track functional, code, and assertion coverage; Debug complex failures in speculation, memory ordering, and TLB/MMU flows; Collaborate with micro-architecture and RTL teams on design clarifications and fixes; Provide guidance and code reviews to junior engineers on testbench design and debug.
Seniority
Senior, hands-on IC
