Stage Ingénieur : Conception Numérique IP et Circuit Intégrés (F/H)
Core
Designing digital logic functions for automotive safety systems, specifically Battery Management Systems (BMS), including power management state machines, communication interfaces, and digital filtering.
Role type
Digital IC Design Intern (RTL)
Builds
Synthesizable Verilog IP blocks for automotive SoCs
Domain
Automotive electronics / Digital IC Design
Required skills
Verilog/SystemVerilog, RTL design, Logic synthesis, Testbench creation, Formal verification, Python/Shell/Tcl scripting, SoC integration
Preferred skills
VHDL, C/SystemC, Digital filtering, Power management state machines
Technologies
Verilog, SystemVerilog, Python, Tcl, Shell, ASIC tools
Responsibilities
Study existing BMS IC solutions, Implement synthesizable Verilog code, Create SystemVerilog testbenches and write assertions, Document RTL design choices and integration guides
Seniority
Intern (final year engineering student)
