Senior Digital IP Design Engineer (f/m/d)
Core
Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), including automotive microprocessors, application processors, and AI/ML cores.
Role type
Senior IC digital IP design engineer
Builds
Interface components, DSP subsystems, and next-generation AI/ML/RISC-V IPs for automotive and networking products
Domain
Semiconductor / Digital SoC Design
Deliverable
production ML models
Required skills
Digital IP design, Mixed-Signal SoC architecture, RTL design (Verilog/SystemVerilog), Design verification (testbench, simulation, debugging), IP synthesis and timing analysis, DFT implementation, AMBA protocols (AHB, AXI, ACE, CHI), Memory systems (ROM, RAM, Flash, DDR/LPDDR), CPU core design (proprietary, RISC-V, AI/ML accelerators), Scripting (Python, Perl, TCL, Shell), Pre-silicon and post-silicon debugging
Preferred skills
AI-based design tools, Conversational German
Technologies
Verilog, SystemVerilog, C/C++, Python, Perl, TCL, Shell, FPGA, Simulation/Emulation tools
Responsibilities
Develop high-quality, area-optimal, low-power RTL designs; Collaborate with hardware, software, and architecture teams to define features and interfaces; Complete design quality checks (Lint, CDC/RDC); Conduct IP-level design verification activities; Perform IP synthesis and timing analysis; Ensure DFT requirements are met; Generate design documentation and participate in reviews; Troubleshoot design issues throughout the lifecycle; Stay updated with industry trends and tools.
Seniority
Senior, hands-on IC
