Precision Analog Data Converter Design
Core
Architect and define next-generation high-resolution, high-speed ADCs and DACs, translating system requirements into detailed architecture and sub-block specifications.
Role type
Senior IC Precision Analog Data Converter Architect
Builds
High-performance data converter ICs (ADCs/DACs) for system-level applications
Domain
Mixed-signal analog design, data conversion architectures
Deliverable
production ML models | product features
Required skills
SAR, Sigma-Delta (DT/CT), Time-Interleaved ADC design, current steering and segmented DAC design, noise shaping, quantization noise analysis, distortion mechanisms, clocking and jitter impact, calibration techniques (background/foreground, DEM, mismatch correction), high-speed analog design (bandwidth, settling, parasitic effects), system-level modeling (MATLAB/Simulink, Verilog-A/AMS), Cadence Virtuoso/Spectre, silicon validation and debug, patentable architecture innovation
Preferred skills
PhD in Electrical Engineering, mentorship of junior designers, cross-functional stakeholder management
Technologies
MATLAB, Simulink, Verilog-A, AMS, Cadence Virtuoso, Spectre
Responsibilities
Drive end-to-end design of data converters including front-end signal conditioning, references, and clocking; Lead detailed circuit design and analysis for critical blocks like comparators, opamps, and reference buffers; Perform deep analysis of performance metrics (SNR, SNDR, SFDR, INL/DNL) and correlate with silicon results; Drive silicon validation, debug, and performance optimization across PVT corners; Serve as technical lead interfacing with system teams and customers; Mentor junior designers in converter design methodologies
Seniority
Senior, hands-on IC with architectural leadership