Senior Principal Analog design engineer
Core
Senior analog design engineer responsible for high-speed Ethernet and SerDes blocks, focusing on transistor-level design of analog building blocks for ultra-low noise performance in CMOS Finfet processes.
Role type
Senior Principal Analog Design Engineer
Builds
Ethernet PHY and switch products
Domain
Automotive Ethernet, High-speed SerDes, Analog IC Design
Deliverable
production ML models | product features
Required skills
Transistor-level analog design, Bandgap references, Current references, OPAMP design, LDO design, Receiver front-end blocks (PGA, CTLE), CMOS Finfet process knowledge, Analog circuit characterization, Yield improvement, ATE characterization, EMC/ESD issue resolution, Cadence Virtuoso, Cadence ADE, SPICE simulation
Preferred skills
Multi-gig Ethernet design experience, Automotive Ethernet experience
Technologies
Cadence Virtuoso, Cadence ADE, SPICE, CMOS Finfet
Responsibilities
Design standard analog building blocks for ultra-low noise performance, Provide innovative analog circuitry solutions for design challenges, Define AFE interfaces and calibrations with system and digital teams, Own analog design execution, performance, and reliability verification, Mentor junior designers on analog circuit design and concepts
