Senior Analog Validation/Characterization Engineer
Core
Develop behavioral models for mixed-signal blocks and perform hands-on lab validation of high-speed transceiver silicon.
Role type
mid-level mixed-signal IC validation and modeling engineer
Builds
behavioral models for chip simulation and validated high-speed transceiver silicon
Domain
automotive semiconductor, mixed-signal IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog (RNM), Verilog-A, Python scripting, mixed-signal simulation (Cadence Virtuoso/Spectre), high-speed lab equipment operation (Oscilloscopes, VNAs, BERTs)
Preferred skills
high-speed serial standards (SerDes, Ethernet, PCIe), structured Product Development Process (PDP) experience, signal integrity concepts (jitter, eye diagrams, insertion loss)
Technologies
SystemVerilog, Verilog-A, Python, NumPy, Matplotlib, PyVISA, Cadence Virtuoso, Spectre, Oscilloscopes, VNAs, BERTs
Responsibilities
Create and maintain behavioral models for mixed-signal blocks; perform bench-top characterization of high-speed transceivers; develop Python scripts to automate lab measurements and generate reports; run mixed-signal co-simulations; collaborate with Design and Verification teams to debug silicon issues
Seniority
Mid-level, hands-on IC