Intern - PEE DIFFUSION
Core
Driving yield improvement initiatives through CMOS matching analysis and Wafer Edge Exclusion (WEE) program to reduce inline mismatches and edge-related yield loss.
Role type
Semiconductor process engineering intern
Builds
Manufacturing yield performance and robust wafer inspection algorithms
Domain
Semiconductor manufacturing / Process engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor process engineering, yield analysis, defectivity characterization, data analytics, statistical analysis, root-cause analysis, inline metrology tools, Wafer Inspection System (WIS) algorithm development
Preferred skills
Cross-functional collaboration, engineering judgment, risk balancing
Technologies
Inline metrology tools, Wafer Inspection System (WIS), data-mining tools
Responsibilities
Conduct fab to fab offload interaction studies to diagnose inline mismatches, perform detailed bevel characterization to assess defectivity, drive WEE performance metrics, troubleshoot process detractors impacting WEE metrics, develop and implement WIS algorithm
Seniority
Intern