Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group
Core
Own and evolve timing-critical circuitry between the NAND array and page buffer, driving designs that impact throughput, timing margin, power, and yield.
Role type
Principal Design Engineer (Non-Volatile Memory)
Builds
Scalable datapath solutions for NAND flash memory
Domain
Semiconductor / Non-Volatile Memory / Analog Mixed-Signal
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CMOS analog/mixed-signal circuit design, device physics fundamentals, high-speed datapath timing analysis, layout parasitics management, SPICE/Fast-SPICE simulation, root-cause analysis for yield issues, design review leadership, mentorship
Preferred skills
NAND/DRAM datapath design experience, wave-pipelining/self-timed/pulse-latched techniques, redundancy/repair architecture, DRAM interface experience (DDR4/5, LPDDR5/6, HBM3/3E/4), CMOS device reliability knowledge
Technologies
SPICE, Fast-SPICE, Monte Carlo analysis, PVT corner analysis
Responsibilities
Define scalable datapath architecture for multi-plane/high-parallelism operation; analyze clock/data timing schemes for long interconnects; drive layout-aware circuit design with parasitic awareness; perform SPICE simulations across PVT, aging, and variability; lead design reviews and mentor engineers; communicate tradeoffs and mitigation plans to integration teams
Seniority
Principal, hands-on IC with technical direction
