Senior Memory Design Engineer, HBM
Core
Design, optimize, and layout digital, analog, and mixed-signal circuits for next-generation memory products.
Role type
Senior IC memory design engineer
Builds
Advanced memory products (DRAM, SRAM, NAND)
Domain
Semiconductor / Memory Technology
Deliverable
production ML models | product features | infrastructure
Required skills
CMOS device physics, analog/digital circuit design, VLSI design, circuit simulation (HSPICE, Spectre), physical build concepts (floor-planning, parasitic extraction, routing, layout verification)
Preferred skills
Memory architecture knowledge (DRAM, SRAM, NAND), silicon debug, reticle experiments, tape-out preparation, Cadence Virtuoso, Verilog/SystemVerilog, sign-off EDA flows
Technologies
HSPICE, Spectre, Cadence Virtuoso, Verilog, SystemVerilog
Responsibilities
Contribute to development, optimization, and layout of Memory, Logic, and Analog circuits; Perform parasitic modeling and support build validation; Coordinate layout process including floor-planning, placement, routing, and physical integration; Conduct circuit modeling and simulation to verify timing, functionality, and reliability; Collaborate across CAD, modeling, standards, and verification groups; Partner with Probe, Test, Product Engineering, Assembly, Marketing, and Process Integration; Propel innovation through contributions to methodologies, architectures, and technologies
Seniority
Senior, hands-on IC