STAFF ENGINEER , Design Verification
Core
Perform analog timing verification for critical paths using circuit-level and mixed-signal simulations to validate setup/hold margins, pulse widths, and skew in memory and storage solutions.
Role type
Staff Engineer, Analog/Mixed-Signal Design Verification
Builds
High-performance DRAM, NAND, and NOR memory and storage products
Domain
Semiconductor manufacturing, Memory and storage solutions
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog or mixed-signal verification, Timing analysis, Circuit validation, CMOS circuit design fundamentals, Analog simulation tools (HSPICE, PrimeSim, FineSim, SpectreFx), Waveform analysis, Timing debug, Verification planning, Root cause analysis
Preferred skills
DRAM or high-speed memory circuits experience, Dynamic timing verification beyond STA, Gate-level simulations, Parasitic effects knowledge, Python scripting for automation, Cross-functional global team collaboration
Technologies
MRUN-based flows, HSPICE, PrimeSim, FineSim, SpectreFx, Verilog, SystemVerilog, Python
Responsibilities
Develop and maintain analog timing testbenches and simulation setups, Execute simulations across PVT corners, Analyze waveforms to identify timing violations and race conditions, Debug timing-related failures and collaborate with design teams, Review design schematics and timing intent, Develop timing verification plans and coverage strategies, Contribute to improvement of verification methodologies and automation, Document verification results and known limitations
Seniority
Staff, hands-on IC with strategic influence