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2026.02_IPDev_Layout_1

Hashimoto, Japan💼 Full-time🗓 2026-05-08 → 2026-07-31

Core

Translating schematics into layout for fabrication reticules and optimizing Memory/Logic/Analog circuits for DRAM products.

Role type

IC layout designer (DRAM)

Builds

DRAM memory chips

Domain

Semiconductor manufacturing / Memory technology

Deliverable

production ML models | product features | infrastructure

Required skills

Schematic-to-layout translation, floor-planning, placement, routing, parasitic modeling, design validation, tape-out procedures, circuit design protocols, fab process knowledge, mask generation techniques

Preferred skills

Cross-group collaboration, issue resolution methodologies, standardization efforts, innovation in memory generations

Technologies

Industry standard simulators, CAD tools, reticle generation systems

Responsibilities

Contributing to new product opportunities by assisting with overall design and optimization; Performing verification processes with modeling and simulation; Overseeing and managing the layout process including floor-planning, placement, and routing; Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability; Proactively soliciting guidance from Standards, CAD, modeling, and verification groups to improve design quality

Seniority

Individual Contributor

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