SR/PRINCIPAL ENGINEER, FE CPIE RAM QUALITY and OPNS ENGINEERING
Core
Establishing strategies, models, and systems to improve wafer at-risk reduction, RAM quality control, and operation efficiency for defense line hardening.
Role type
Senior/Principal Process Integration Engineer (RAM Quality & Operations)
Builds
RAM memory and storage solutions for data centers, AI, 5G, and mobile applications
Domain
Semiconductor manufacturing (Memory/Storage)
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Wafer at-risk modeling, Failure Mode Effect Analysis (FMEA), Statistical Process Control (SPC), defect analysis tools, SQL, programming languages, project management
Preferred skills
Product and test wafer capacity modeling, Tableau creation, Organization Change Management, international travel
Technologies
SQL, Tableau, SPC tools, defect analysis tools
Responsibilities
Establish strategies to reduce defect OOC% variation, lead the Copy Smart Team to align RAM network strategy, perform audits and establish compliance metrics, track Fab performance metrics for benchmarking, provide tactical support for yield, quality, and cycle time issues
Seniority
Senior/Principal, hands-on IC with strategic leadership
