ASIC Physical Design Engineer (RDSS Intern)
Core
Physical design of digital chips from RTL frozen to tape out, focusing on synthesis, formal verification, timing closure, and flow automation.
Role type
ASIC Physical Design Engineer (Research and Development Substitute Services Intern)
Builds
High-performance digital chips for AI, GPUs, and accelerated computing
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features
Required skills
RTL design, netlist generation, synthesis, formal verification, timing closure, constraints definition, EDA tool usage (Synopsys/Cadence), Python/TCL scripting
Preferred skills
Chip integration, floorplanning, cross-team collaboration, flow automation development
Responsibilities
Chip integration and netlist generation, Synthesis, RTL/netlist quality check, Formal Verification, Constraints creation and validation, Timing closure for partition and full chip levels, Function eco creation, Flow automation development
Seniority
Intern
