ASIC Design Engineer, Clocks
Core
Designing high-frequency, low-power clocking architectures for NVIDIA GPUs to support consumer graphics, self-driving cars, and AI workloads.
Role type
Senior ASIC Design Engineer (Clocks)
Builds
GPU clocking RTL and netlists for high-performance silicon
Domain
Semiconductor / GPU / High-Speed Digital Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog), logic synthesis, scripting (Perl/Python), sub-micron silicon noise analysis, cross-talk mitigation, OCV effects understanding, DFT implementation, on-chip clocking networks
Preferred skills
Backend flow expertise, SOC verification collaboration, silicon bug debugging
Technologies
Verilog, Perl, Python
Responsibilities
Collaborate with frontend and backend teams to define clocking requirements; architect and validate clocking RTL; run and enhance in-house flows for RTL and netlist quality; drive issue resolution; deliver clock information to SOC verification, timing, and DFT teams; debug GPU clock silicon bugs with software and silicon solution teams
Seniority
Senior, hands-on IC
