Senior Manager, DPU Performance and System Validation
Core
Lead a team of 25+ engineers to define Performance Verification plans, coordinate performance emulation and system validation, and manage post-silicon debugging for DPU chips.
Role type
Senior Manager, DPU Performance and System Validation
Builds
DPU chips for innovative computing
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Performance management in chip build, DPU performance expertise, System validation, Post-silicon debugging, Cross-functional collaboration, Team leadership
Preferred skills
None stated
Technologies
None stated
Responsibilities
Lead and manage a group of 25+ engineers, Coordinate the performance emulation and functional validation processes, Participate in post-silicon performance debugging, Develop and unify performance debug processes across all platforms
Seniority
Senior, hands-on IC
