CareerPlan

Process Engineer Senior

Off-Campus: Mesa/TempeFull-time$120k2026-08-31 → 2026-11-10

Core

Lead process development and equipment ownership for 300mm wafer-level packaging tools, specifically focusing on fanout packaging processes including photolithography, panelization, molding, dicing, and grinding.

Role type

Senior IC process engineering lead (semiconductor advanced packaging)

Builds

Robust wafer packaging processes and equipment solutions for device physics, deposition, etching, and electrical test teams

Domain

Semiconductor manufacturing / Advanced packaging

Required skills

Statistical process control, data analysis, equipment maintenance, process development, IP development, team supervision, procedure writing, cross-training, conflict resolution

Preferred skills

Molding, grinding, die attach, ball drop, wafer saw operation, active matrix TFT processing, amorphous-silicon processes, thin film processing, JMP or Minitab, semiconductor advanced packaging experience

Technologies

300mm wafer packaging toolsets, JMP, Minitab

Responsibilities

Maintain equipment operations and increase uptime, respond to production issues, develop new processes and identify improvements, supervise a team of 3-4 engineers and technicians, interact with students and faculty to provide technical services, write safety procedures

Seniority

Senior, hands-on IC with team leadership