Intern - DRAM Test Structure Design and Layout Engineering
Core
Develop, layout, verify, and analyze semiconductor test structures (TEGs) to characterize advanced DRAM technologies and support silicon evaluation.
Role type
Engineering Intern (Semiconductor Test Structure Design & Layout)
Builds
Semiconductor test structures (TEGs) for advanced DRAM nodes
Domain
Semiconductor manufacturing / DRAM technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Semiconductor device fundamentals, circuit fundamentals, Python/Tcl/Perl scripting, DRC/LVS verification, data analysis, technical reporting
Preferred skills
VLSI build experience, EDA tools (Cadence Virtuoso, Calibre), layout editing, physical build verification concepts, data visualization
Technologies
Python, Tcl, Perl, Cadence Virtuoso, Calibre, EDA tools
Responsibilities
Develop and arrange semiconductor test structures for advanced DRAM nodes; Support physical verification activities including DRC and LVS; Perform device and process simulation to predict electrical behavior; Develop and analyze test structures for device characterization and technology qualification; Write automation scripts to increase engineering efficiency; Collaborate with technology development and process integration teams; Document methodologies and results for future projects
Seniority
Intern
