Senior Engineer/ Engineer – PDE Process Control Systems
Core
Define global DL4 matrices, ensure site alignment, drive automation/AI enhancements, and oversee test specifications for semiconductor device reliability.
Role type
Senior IC engineer (semiconductor device physics & test analytics)
Builds
Global defense line 4 (DL4) workflows, automated detection systems, and standardized test programs for memory/storage devices.
Domain
Semiconductor manufacturing, device physics, and reliability engineering
Deliverable
production ML models | product features
Required skills
semiconductor device physics, device modelling and simulation (TCAD, Silvaco, Sentaurus), compact modelling, circuit-level analog analysis (HSPICE), electrical test data analysis, root cause analysis for package/device failures, data analytics, scripting, statistical modeling (Python, MATLAB, JMP, SQL)
Preferred skills
M.Tech in Electrical/Electronics Engineering with project experience in semiconductor packaging, test, and reliability
Technologies
TCAD, Silvaco, Sentaurus, HSPICE, Python, MATLAB, JMP, SQL
Responsibilities
Define global DL4 matrices (turnaround time, overdue matrices, detection compliance, SBL reactions), drive global automation and AI enhancements (YIT, Auto-contain, auto-disposition, SMAI), monitor Assembly and Test specifications, perform root cause analysis for failures, review and release test programs, collaborate with cross-functional teams to enhance defense line 4 capabilities
Seniority
Senior, hands-on IC
