EUV Mask BEOL R&D Engineer
Core
Developing EUV mask Back-End-of-Line (BEOL) technologies and characterization processes to enable next-generation DRAM manufacturing.
Role type
Senior IC R&D Engineer (Semiconductor Lithography/Mask Technology)
Builds
High-NA EUV mask solutions and process integration for advanced memory nodes
Domain
Semiconductor manufacturing, specifically EUV lithography and mask technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EUV mask BEOL characterization, actinic inspection, automated defect classification, printability assessment, physics-based modeling, lithography simulation, supplier engagement, technology roadmap definition, BEOL process engineering transition
Preferred skills
EUV/High-NA mask/wafer technology experience, lithography fundamentals, OPC, advanced mask design, yield and defectivity management, complex R&D leadership
Technologies
EUV systems, High-NA lithography, lithography simulation tools, actinic inspection equipment, metrology tools
Responsibilities
Develop actinic inspection and defect repair processes; drive physics-based modeling to correlate mask properties with wafer performance; define tool capability requirements and lead early supplier engagement; transition developed technologies to BEOL process engineering teams
Seniority
Senior, hands-on IC with strategic guidance