SR Layout Engineer, DEG
Core
Design and development of IP layouts for DRAM chips, ensuring high-quality physical designs and on-time delivery.
Role type
Senior IC analog layout engineer (DRAM)
Builds
Block-level and sub-block-level physical layouts for DRAM memory products
Domain
Semiconductor / Memory / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Virtuoso, DRC/LVS/EM verification, Critical Analog Layout design, Circuit Design principles, Analog Layout fundamentals (matching, EM, latch-up, IR-drop)
Preferred skills
DRAM/memory circuits experience, large-scale hierarchical designs, parasitic extraction flows, post-layout optimization
Technologies
Cadence Virtuoso
Responsibilities
Design and develop IP layouts for DRAM chips; Perform layout verification (LVS/DRC/EM); Guide and lead team members in sub-block-level layout execution; Contribute to project management; Communicate with global engineering teams
Seniority
Senior, hands-on IC
