AI Hardware Engineering Intern
Core
Intern analyzing AI inference behavior, memory movement, and hardware/software co-design to optimize throughput, latency, and power consumption for GenAI workloads.
Role type
AI Hardware Engineering Intern
Builds
AI inference pipelines, cluster architectures, and silicon designs for CPUs, GPUs, and AI accelerators.
Domain
Semiconductor hardware, AI infrastructure, and high-performance computing
Deliverable
production ML models
Required skills
Computer architecture, distributed systems, C/C++/Rust/CUDA programming, transformer model inference, memory hierarchy management, benchmarking, system simulation
Preferred skills
VLSI/ASIC/FPGA design, compiler/kernel development, PyTorch/vLLM/TensorRT-LLM, Linux/Kubernetes, RDMA/InfiniBand, RTL/FPGA prototyping
Technologies
PyTorch, vLLM, SGLang, TensorRT-LLM, Triton, Kubernetes, CUDA, SYCL, OpenCL, RDMA, InfiniBand, CXL, PCIe, NVMe
Responsibilities
Conduct technical research on next-gen AI infrastructure (CPUs, GPUs, ASICs, networking); Analyze GenAI workloads (transformers, MoE, multimodal) for hardware implications; Evaluate hardware behavior of inference pipelines (prefill/decode, KV-cache, memory bandwidth); Identify product gaps in hardware capabilities and tooling; Develop technical recommendations and benchmarks for AI customer requirements; Build models/simulations to evaluate hardware/software trade-offs; Investigate system bottlenecks across compute, memory, and networking; Engage with AI software ecosystem partners and ISVs; Present findings via architecture diagrams and technical reports.
