Senior ASIC DFT Engineer
Core
Define DFT architecture, strategy, and implementation for complex AI acceleration IPs and subsystems to ensure test coverage, area, timing, and power balance.
Role type
Senior IC ASIC DFT Engineer
Builds
AI hardware chips and subsystems
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
DFT architecture definition, scan insertion, test compression, boundary scan (JTAG), MBIST, ATPG, pattern generation, silicon bring-up, cross-functional collaboration
Preferred skills
Hierarchical DFT, low-power test, in-system test, silicon debug, AI tool adoption in DFT flows
Technologies
ATPG tools, JTAG, MBIST frameworks
Responsibilities
Define DFT architecture and strategy for complex AI acceleration IPs; Build DFT implementation (scan, compression, boundary scan, MBIST) and drive fault coverage closure; Lead ATPG & pattern generation; Contribute to DFT methodology development; Champion AI tool usage in DFT flows; Collaborate with design, verification, and physical design teams for silicon bring-up and yield analysis
Seniority
Senior, hands-on IC
