SMTS ASIC Digital Design
Core
Own hardware safety analysis and design safety mechanisms for ARC MIPS processor IP and Custom Silicon SoCs, ensuring compliance with ISO 26262 for automotive systems.
Role type
Senior IC functional safety engineer (ASIC/SoC)
Builds
Safety-certified processor IP and SoC-level safety architectures for automotive radar, ADAS, and control applications
Domain
Semiconductor / Automotive Functional Safety
Required skills
FMEDA, DFMEA, DFA, FTA, RTL analysis (Verilog/SystemVerilog), microarchitecture reasoning, safety metrics derivation (SPFM, LFM, PMHF), fault injection planning, safety mechanism definition (ECC, parity, lockstep, watchdog), traceability management
Preferred skills
ISO 26262/IEC 61508 certification, SEooC integration, fault simulation tooling (VC Z01X), Python/TCL scripting, VCS/Verdi debugging, UPF, ISO/SAE 21434, RISC-V architecture
Technologies
Verilog, SystemVerilog, VCS, Verdi, VC Z01X, Python, TCL, Jama, FPGA
Responsibilities
Perform hardware safety analysis (FMEDA, DFMEA, DFA, FTA) for processor IP and SoCs; Define and verify safety mechanisms at RTL level; Plan and interpret fault injection campaigns; Derive and track safety metrics; Produce safety work products (manuals, reports, safety cases); Maintain traceability from requirements to verification evidence; Support ISO 26262 assessments
Seniority
Senior, hands-on IC
