Quantum TSV Integration Engineer
Core
Own development and integration of cryogenic, superconducting TSV technologies enabling high-density vertical interconnects for scalable quantum packaging from concept through manufacturing.
Role type
R&D TSV Integration Engineer (Quantum Advanced Packaging)
Builds
Cryogenic 3DHI roadmap and APPC capability build-out for quantum systems
Domain
Semiconductor manufacturing / Quantum computing / Advanced Packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
TSV process development, superconducting liner design, dielectric isolation schemes, via geometry optimization, cryogenic thermal/mechanical stability analysis, end-to-end integration flows, process qualification, root-cause analysis, materials selection for superconducting operation, tool definition (DRIE, PVD/CVD/ALD), yield improvement strategies
Preferred skills
PhD in relevant field, prior leadership experience, project management, innovation in ambiguous environments
Technologies
Nb, Al-based superconducting liners, DRIE, PVD, CVD, ALD, wafer thinning, RDL, bump/interconnect layers
Responsibilities
Lead development of TSV processes for cryogenic/superconducting applications; Define TSV architectures including liners, dielectrics, and geometries; Optimize designs for low-loss electrical/RF transport and cryogenic stability; Own end-to-end integration flows from etch to packaging stacks; Drive process integration for prototyping and qualification; Support characterization of signal integrity and thermal leakage; Identify and analyze failure modes; Collaborate with materials and device teams; Define requirements for process tools; Drive next-generation TSV scaling strategies; Contribute to IP and publications
Seniority
Senior, hands-on IC with R&D leadership
