Logic Design Engineer
Core
Designing configurable, low-latency RTL and optimizing FPGA logic & timing for quantum computing control systems.
Role type
Senior IC logic design engineer (FPGA/RTL)
Builds
State-of-the-art control and orchestration platform for quantum computers
Domain
Quantum computing hardware control
Required skills
RTL coding, System Verilog, FPGA logic optimization, timing optimization, hardware/software interface design
Preferred skills
VCS, Vivado
Responsibilities
Designing configurable and low-latency RTL, optimizing FPGA logic and timing, owning the end-to-end coding process from architecture to implementation, learning system and software requirements for HW-SW interface implementation
Seniority
Senior, hands-on IC
