Senior Verification Engineer
Core
Building verification environments and test infrastructure for full-stack quantum computer control systems with strong HW-SW coupling.
Role type
Senior IC verification engineer (hardware/software)
Builds
Production verification environments, test plans, and reference model integrations for quantum control hardware
Domain
Quantum computing hardware and control systems
Required skills
UVM, System Verilog, verification IP, PCIe, DDR, AXI protocols, C/C++/Python/System C, test plan definition, verification flow design
Preferred skills
HW/SW interaction understanding, creating verification environments from scratch, reference model integration
Technologies
UVM, System Verilog, C, C++, Python, System C, PCIe, DDR, AXI
Responsibilities
Creating verification environments from scratch (drivers, monitors, coverage), VIP (DDR/PCIe/AXI) integration, defining verification sequences via complex control-flow constraints, system understanding of full-stack product with strong HW-SW coupling, reference model integration, test plan definition, defining verification flows and creating supporting infrastructure
Seniority
Senior, hands-on IC