Sr. Debug Engineer - PCIe/CXL, RAS, Memory
Core
Senior Systems Debug Engineer driving root cause resolution for customer failures in server systems, focusing on silicon and system engineering expertise.
Role type
Senior IC systems debug engineer (server)
Builds
High-quality, industry-leading server technologies and debug solutions for customers
Domain
Semiconductor / Server Systems / Hardware Debug
Required skills
RAS validation and debug, PCIe/CXL protocol debug, Memory functional and protocol validation, MCA/MCE validation and debug, post silicon validation methodologies, Python scripting, high-speed test and measurement equipment usage, X86 micro architecture knowledge, debug techniques and methodologies
Preferred skills
Experience with protocol analyzers and scopes, experience with debug scripts and tools (SCAN, JTAG), experience with SOC program bring-up and validation
Technologies
Python, C++, Perl, Ruby, SCAN, JTAG, Protocol Analyzers, Scope, PCIe, CXL, RAS, MCA, MCE, X86
Responsibilities
Working on RAS, PCIe, Memory, MCA, CXL and Micro-Controller related failures with customers, Collaboration with AMD global teams to identify best solutions, Providing validation and debug recommendations to customers, Utilizing debug tools to narrow down and root cause customer failures, Debugging issues found during bring-up, validation, and production phases of SOC programs, Leading task force and collaborative approach with multiple teams
Seniority
Senior, hands-on IC
