2026 Graduate Trainee - Silicon Design Engineer (December Intake)
Based in Malaysia
Core
Verify new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) and run design flows and simulations.
Role type
Graduate Trainee Silicon Design Engineer (Verification)
Builds
High Speed IO Protocol IPs for AMD processors
Domain
Semiconductor / Hardware Design
Required skills
Verification planning, simulation, regression management, debugging, scripting
Preferred skills
System Verilog, Verilog, Perl, TCL, Python, AI tools
Technologies
USB, PCIe, Ethernet, UFS, System Verilog, Verilog, Perl, TCL, Python
Responsibilities
Plan, build, and execute verification of High Speed IO Protocol IPs; Run design flows, simulations, and regression management; Perform first-level debug of test/design errors; Develop scripting for task execution efficiency
Seniority
Entry-level Graduate Trainee
