Sr. Debug Engineer - PCIe/CXL, RAS, Memory
Core
Drive accurate, scalable, and complete solutions for customer issues related to RAS, PCIe, Memory, MCA, CXL, and Micro-Controller failures in AMD server systems.
Role type
Senior Server Systems Debug Engineer (Silicon & System Engineering)
Builds
Industry-leading server technologies and debug solutions for customers
Domain
Semiconductor / Server Systems / Hardware Debug
Required skills
RAS validation and debug, PCIe/CXL functional and protocol debug (Gen1-Gen6), Memory functional and protocol validation/debug, MCA/MCE validation and debug, post silicon validation methodologies, X86 micro architecture knowledge, high-speed test and measurement equipment handling, Python/C++/Perl/Ruby scripting, debug techniques and methodologies
Preferred skills
Experience with protocol analyzers and scopes, experience with debug scripts and tools (SCAN, JTAG), experience with SOC program bring-up, validation, and production phases
Technologies
Python, C++, Perl, Ruby, SCAN, JTAG, Protocol Analyzers, Scope, PCIe, CXL, RAS, MCA, MCE, X86, SOC
Responsibilities
Working on RAS, PCIe, Memory, MCA, CXL and Micro-Controller related failures with customers to get problems resolved, Collaboration with AMD global teams to identify best solutions, Providing validation and debug recommendations to customers, Utilizing debug tools to narrow down and root cause customer failures, Debugging issues found during the process, bring-up, validation, and production phases of SOC programs, Engaging in other software/hardware/design teams, Leading task force and collaborative approach with multiple teams
Seniority
Senior, hands-on IC
