Platform Validation Lead - IO Interfaces
Core
Lead post-silicon validation and debug for datacenter CPU and AI systems, focusing on high-speed IO interfaces (PCIe, CXL, RAS) and leveraging AI/ML for test automation.
Role type
Senior IC systems validation engineer (IO interfaces)
Builds
High-quality datacenter CPU and AI GPU systems
Domain
Semiconductor / Datacenter Hardware
Deliverable
production ML models
Required skills
System-level validation, IO interface expertise (PCIe, CXL, RAS), SoC debugging, test plan development, root cause analysis, board/platform-level debug, scripting (C/C++, Python, Perl), hardware capture tools (oscilloscopes, protocol analyzers, JTAG)
Preferred skills
Linux/Windows OS proficiency, pre-silicon verification/emulation knowledge, silicon bring-up experience
Technologies
PCIe, CXL, RAS, Linux, Windows, C/C++, Python, Perl, Oscilloscopes, Protocol Analyzers, JTAG
Responsibilities
Develop and execute feature enablement and validation test plans for SoC and system-level features; Leverage AI/ML technologies to enhance post-silicon validation, debug, and test automation efficiency; Develop test content for focus testing and system-level stress testing of IO domains; Collaborate with partners to provide root cause analysis for platform issues in a Datacenter environment; Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
Seniority
Senior, hands-on IC
