ATE Test Engineer
Core
Develop and advance wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8 to improve test quality, yield, and release readiness for next-generation microprocessor and chiplet products.
Role type
Senior ATE Test Engineer (Infrastructure & Strategy)
Builds
Reusable wafer-sort Base Test Program, common Test Shell, and test flows for AMD processors
Domain
Semiconductor manufacturing / Advanced Packaging / Microprocessors
Required skills
Advantest V93000 platform expertise, SmarTest 8, Java, C++, Python, Perl, Linux/Unix, revision control, test flow development, pattern integration, timing analysis, margining, diagnostics, chiplet architecture knowledge, 2.5D/3D packaging, link training, bit-error-rate testing
Preferred skills
ORE offline simulation, AI-enabled workflows, global team leadership, mentorship
Technologies
Advantest V93000, SmarTest 8, PCIe, CXL, UCIe, Ethernet, JESD204, USB, DDR, HBM PHY, xGMI, Infinity Fabric, UPI, NVLink
Responsibilities
Develop and integrate reusable wafer-sort Base Test Program and common Test Shell infrastructure; Lead SmarTest 8 and Advantest V93000 test program development, debug, validation, and production support; Drive wafer-sort strategy, first-silicon bring-up, characterization, and margining; Troubleshoot complex interactions across silicon, test software, and hardware; Partner with Design, Yield, and Manufacturing teams to improve coverage and yield; Define scalable architecture and coding practices for reuse across products and sites.
Seniority
Senior, hands-on IC with architectural influence
