Principal Chip Lead, Silicon Co-Design Group
Core
Technical lead for high-consequence silicon programs, accountable for end-to-end technical integrity and guiding co-design feature integration across architecture, design, validation, and manufacturing.
Role type
Principal, strategy & mentorship (Silicon Co-Design)
Builds
Datacenter, Gaming, Robotics, Automotive, and Embedded chips (SoC/ASIC)
Domain
Semiconductor / Silicon Design
Deliverable
production ML models
Required skills
SoC and ASIC architecture, post-silicon bring-up, validation, system integration, HBM, SerDes, power and thermal, packaging, multi-functional bug resolution, technical narrative shaping, cross-functional leadership without direct authority
Preferred skills
Flagship GPU/AI accelerator/CPU/networking ASIC experience, patents or conference papers, reusable methodology/playbooks, AI tool usage for team velocity
Responsibilities
Serve as single technical point of contact for multi-functional decisions; Co-lead program-level feature integration from chip to system; Resolve hardest multi-functional bugs (HBM, power, thermal, I/O, packaging); Steward qualification playbook and capture lessons; Shape technical narrative for executive leadership; Mentor Chip Leads and contribute to SCG-wide methodology; Lead Critical Debug and SCG Technical Execution forums
Seniority
Principal, strategy & mentorship
