Senior Physical Design Engineer
Core
Drive physical design and timing closure from netlist to GDS for GPU chips, integrating analog IOs and macros.
Role type
Senior Physical Design Engineer (IC)
Builds
GPU chips
Domain
Semiconductor / VLSI Design
Deliverable
production ML models
Required skills
Physical design flow, Timing closure, DRC/ERC/LVS verification, RC extraction, IR drop analysis, EM analysis, ECO implementation, Formal verification, Synopsys/Cadence tools, Automation scripting
Preferred skills
Scan insertion, DFT knowledge
Technologies
Synopsys, Cadence
Responsibilities
Drive physical design and timing from netlist to GDS; Partner with mixed signal teams to integrate Analog IOs and macros; Perform multi-mode/multi-corner timing closure, RC extraction, cross-talk, IR drop, and EM analysis; Work with front-end teams to create and update timing constraints; Perform physical verification (DRC, ERC, LVS, Antenna checks); Debug timing violations and implement functional, timing ECOs and perform formal verification.
Seniority
Senior, hands-on IC