Sr. Systems Design Engineer
Core
Designing and maintaining advanced debug infrastructure for AMD's client, graphics, and custom product lines, enabling end-to-end debug capabilities including on-chip instrumentation, JTAG over USB-C, and automated data capture.
Role type
Senior Systems Design Engineer (Silicon Debug Infrastructure)
Builds
Debug tooling, automated data collection pipelines, IP inspection libraries, and server-side analysis services for silicon bring-up and validation.
Domain
Semiconductor / Hardware Engineering / Debug Infrastructure
Required skills
JTAG hardware and software, Python, low-level data manipulation, containerized tools, large-scale automation, system-level debugging, firmware development, IP block analysis, CI/CD pipelines, Kubernetes, USB protocols, Linux, microprocessor-based debug.
Preferred skills
x86 system architecture, SOC internal architecture, BIOS, platform design, validation methodologies, C, Java, JavaScript.
Technologies
JTAG, Python, Kubernetes, Linux, USB, CI/CD, ADS (Automated Debug System), K8 containers.
Responsibilities
Study upcoming SOCs to identify needs for advanced debug tools; work with IP teams to acquire functional understanding of IP blocks; instrument debug data into mission mode firmware; write specs for debug data collection in in-chip microcontrollers; build Python libraries to capture debug data and evaluate IP block health; contribute to JTAG tools hardware and software development; build and monitor automated QA execution of debug tools as CI/CD pipelines; assist in constructing K8 containers for debug services; work with regional Customer Engineering teams to enable debug features in end-customer designs; work with IT and InfoSec to enable secure VPN tunnels for JTAG devices.
Seniority
Senior, hands-on IC
