CareerPlan

FabVantage Defect Technologist

Santa Clara,CAFull-time$124k–$171k2026-10-13 → 2026-10-23

Core

Design and optimize manufacturing processes for display and semiconductor technologies, focusing on defect data collection, analysis, and troubleshooting to reduce defect baselines for the field.

Role type

Senior IC process engineer (defect technology)

Builds

Defect troubleshooting trees, knowledge bases (Zero Defect, DES), technical documentation, and training content for field deployment.

Domain

Semiconductor manufacturing / Display technology / Materials science

Required skills

Defect troubleshooting methodologies, Semiconductor equipment knowledge (Dielectric Deposition, Etch, Metal Deposition), Fab leadership experience, Data analysis, Cross-functional collaboration

Preferred skills

Surface/material analysis (SEM/FIB/TEM/AFM, EDX/XPS/Auger, XRD/XRF/Raman/FTIR), Particulate mechanics and transport, Plasma and vacuum technology

Technologies

DefectRx, DefectExpert System (DES), DES auto-classification

Responsibilities

Design DefectRx data collection plans and failure analysis strategies; Validate data collected by field engineers and verify DES auto-classification; Develop and assist development of troubleshooting trees by equipment type; Build and maintain knowledge bases for multiple equipment types; Contribute to training and communication documents for field deployment; Participate in Defect CoE cross-organizational learning forums

Seniority

Senior, hands-on IC