CareerPlan

FabVantage Defect Technologist

Santa Clara,CA, USFull-time$124k2026-10-13 → 2026-11-10

Core

Design and optimize manufacturing processes for display and semiconductor technologies, focusing on defect data collection, analysis, and troubleshooting to reduce defect baselines.

Role type

Senior IC process engineer (defect management)

Builds

Defect troubleshooting trees, knowledge bases (DefectRx/DES), and training content for field deployment

Domain

Semiconductor manufacturing / Display technology

Required skills

defect troubleshooting methodologies, semiconductor equipment knowledge (Dielectric Deposition, Etch, Metal Deposition), leading memory or logic fab experience, data analysis, hardware characterization, technical documentation

Preferred skills

surface/gas species/material analysis (SEM/FIB/TEM/AFM/EDX/XPS/Auger/XRD/XRF/Raman/FTIR/RGA/OES), particulate mechanics and transport, plasma and vacuum technology

Technologies

DefectRx, DefectExpert System (DES), SEM, FIB, TEM, AFM, EDX, XPS, Auger, XRD, XRF, Raman, FTIR, RGA, OES

Responsibilities

Design DefectRx data collection plans and failure analysis strategies; validate data and verify auto-classification errors; develop and maintain troubleshooting trees; build and curate defect knowledge bases; write case studies and technical bulletins; collaborate with cross-functional teams and field engineers

Seniority

Senior, hands-on IC