端侧NPU架构师 - PICO
Core
Design and evolve end-side NPU architecture to ensure high energy efficiency for model inference under low-power constraints.
Role type
Senior IC NPU Architect
Builds
End-side NPU IP for XR platforms (VR/AR)
Domain
Consumer electronics / Edge AI
Deliverable
production ML models
Required skills
Computer architecture, SIMD/vector/matrix unit design, Dataflow architecture, Systolic arrays, On-chip/off-chip memory optimization, Low-power design, Neural network quantization, Model pruning, Sparse computing, Operator fusion, Memory allocation, Instruction scheduling, Hardware-software co-design
Preferred skills
End-side large model hardware acceleration, KV Cache compression, Long-text processing, SoC NPU IP tape-out and mass production
Technologies
NPU IP, SoC, XR platforms
Responsibilities
Define PPA metrics and architecture evolution roadmap; Analyze operator and dataflow characteristics of mainstream edge AI models; Evaluate performance/power and explore design space; Collaborate with algorithm and design teams for full lifecycle delivery from definition to mass production.
Seniority
Senior, hands-on IC
