Senior System Level Verification Engineer
Core
Develop system-level test environments for complex ARM-based SoC hardware, including simulation, emulation, ROM/FW bringup, and debugging.
Role type
Senior System Level Verification Engineer (SoC/ASIC)
Builds
System-level test environments, test plans, and test cases for SoC ASIC chips
Domain
Semiconductor / Hardware Verification / SoC Design
Required skills
System level verification, C programming, RTL debugging, test planning, device modeling (JTAG, UART, SPI, I2C), waveform analysis, scripting (Python, Perl, Shell, Make), root cause analysis
Preferred skills
Emulation/FPGA/post-silicon validation, IP interface validation (USB, Ethernet, PCIe, DDR), AI tools for test planning, SPDM/PLDM/MCTP protocols, Caliptra/Crypto APIs, bootloader/firmware development, firmware authentication/OTP provisioning
Technologies
ARM, C, Python, Perl, Shell, Make, JTAG, UART, SPI, I2C, RTL, Confluence, Jira, FPGA, Emulators
Responsibilities
Develop SOC system level test environment for simulation and emulation; Develop testplan and tests including error and stress tests; Run and debug tests in regressions; Work with other teams in root-causing HW issues; Validation ROM; Work with SW team in debugging device driver issues and OS boots
Seniority
Senior, hands-on IC
