Principal Engineer, RTL Design
Core
Lead integration of complex multi-billion transistor SoCs comprising CPUs, GPUs, NPUs, AI accelerators, memory subsystems, and high-speed peripherals.
Role type
Principal RTL Design Engineer (SoC Architecture & Integration)
Builds
Scalable SoC architectures, NoC solutions, heterogeneous compute systems, and low-power hardware designs
Domain
Semiconductor / SoC Design / Hardware Architecture
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog RTL design, SoC architecture, AMBA protocols (AXI, AHB, APB), UPF/low-power design, clock/reset architecture, CDC/RDC methodologies, EDA tools for synthesis and timing analysis, functional safety (ISO 26262), hardware security architecture
Preferred skills
Experience with UCIe, PCIe, DDR/LPDDR, CXL, Ethernet, High-speed SerDes, formal verification techniques, static/dynamic checks
Technologies
Verilog, SystemVerilog, UPF, AMBA, ISO 26262, EDA tools
Responsibilities
Lead top-level RTL integration and IP assembly, architect NoC solutions for high-bandwidth data movement, define clocking and reset strategies across complex interconnect fabrics, implement hardware architectures supporting functional safety and security, drive power-aware RTL integration and verification, provide technical leadership and mentoring to RTL engineers
Seniority
Principal, hands-on IC with strategic influence
